Interface pn junction arrays with high yielded grown p-Si microneedles by vapor–liquid–solid method at low temperature

Abstract

In this work we report the fabrication and investigation of the properties of interface pn junction arrays formed at the interface of vertically aligned p-Si microneedles and n-Si substrate. Arrays of boron doped p-Si microneedles were grown on n-Si substrate with the maximum yield of 100% by Au-catalysed vapor–liquid–solid (VLS) growth using in-situ doping with the mixed gas of Si2H6 and B2H6 at temperature less than 700°C, which is low as compared to the temperature (1100°C) required by diffusion process to dope Si microneedles after VLS growth. The physical dimension (diameter, length) and position of these p-Si microneedles can be controlled. The variation of growth rate, diameter, conductivity, impurity concentration and hole mobility of these p-Si microneeedles were investigated with the variation of boron doping. The pn junctions, formed with p-Si microneedles having different diameters, were found to exhibit standard diode characteristics. These pn junction embedded Si microneedle arrays might be potential candidate in sensor area applications. Again, low temperature processing would be compatible to integrate these junction arrays with other circuitry on a chip. This work provides one step forward to realize more sophisticated vertical active devices (BJT, MOSFET, etc) with Si microneedles.