Interface and oxide state behaviors of commercial n-channel power MOSFETs during high electric field stress and thermal annealing at 150 °C

Abstract

The states in the gate oxide (fixed oxide traps), near the gate oxide/substrate interface (slow switching traps/border traps), and states at this interface (fast switching traps/true interface traps), formed by high electric field stress (HEFS) in commercial n-channel power MOSFETs, have been investigated. The midgap technique (MGT) and charge-pumping technique have been applied for that purpose. However, the subthreshold characteristics have been destroyed during the positive HEFS, and MGT could not be applied, but they have not been destroyed during the negative HEFS. The transistor trap densities have shown the high reproducibility within ±5%. Some transistors showed high resistivity to the HEFS with negative gate currents, even up to −0.1 A, and the gate voltages during those experiments reached ≈−70 V. Spontaneous annealing of ΔNft and ΔNst (MG) after negative HEFS was very high (about 50%), reaching saturation after ≈100 h. The transistors have shown rapid and intensive annealing at 150 °C after negative HEFS, and more than 80% defects have been annealed in less than 1 h.