Abstract
The drive to increase the functionality and performance of electronic products has resulted in the need to increase the density of every element of the electronics assembly from the silicon chip, which has relentlessly reduced in size, to the printed circuits used in their interconnection. Accompanying the reduction in feature sizes on IC chips has been an explosion in pin counts, especially in high‐end microprocessors. The challenge thus falls to the electronics interconnection and packaging industry to allow the pace to continue. Reviews strategies being either proposed or used to meet the challenge of high‐density interconnection at both chip package and next level substrate.
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