Study and application of wright etch in sub-quarter-micron technology

Abstract

It is a well-known fact that stacking faults and crystalline defects in silicon wafers have impact the yield of the wafers. However as microelectronic devices scale down into deep sub-micron regime, there are reduction in the feature sizes of the transistors. This reduction in feature sizes has determine the size of the defect that have impact on the devices. In this paper, the timing of wright etch to correctly delineate stacking faults and silicon defects on chips of different technologies was evaluated. The application of wright etch to delineate the silicon defect localized by contact-level passive voltage contrast (PVC) technique in 0.18/spl mu/m and 0.13/spl mu/m technologies would be discussed too. This kind of silicon defect was also confirmed by cross-sectional transmission electron microscope analysis (XTEM).