Interconnection optimized path metric access scheme for k/n-rate viterbi decoders

Abstract

Path metric computation in Viterbi decoders is a crucial task where previously computed path metrics are used as input values. If an area-efficient decoder is preferred, mapping the Viterbi algorithm onto reduced computational resources becomes attractive. This implies a need for path metric storage and an interconnection network between parallel computation units and path metric memories. In this paper, an efficient access scheme for path metric computations is presented, which reduces the interconnection complexity. The scheme supports different code rates, number of states, and parallelism of the decoder. It utilizes an in-place update method resulting in minimum path metric memory usage. Further memory savings are achieved by merging several path metrics into one memory word, which reduces the number of memory modules. The interconnections have been simplified reducing the number of connection patterns with efficient scheduling of path metric computations. With certain design parameters, a simple hardwired interconnection network is achieved.