An efficient approach for in-place scheduling of path metric update in Viterbi decoders

Abstract

The in-place path metric updating is a well-known technique for efficiently dealing with the management of path metric memory in Viterbi decoders. In this paper, we present a simple but efficient technique to partition the path metric memory into 2/sup i/ banks and then distribute a set of path metrics into scheduled add compare select (ACS) units. Results show that applying the presented scheduling technique the equivalent memory bandwidth can be increased with limited hardware overhead. The resulting architecture has the following characteristics: (1) the interconnection overhead between ACS units and the memory bank structure can be significantly reduced, (2) the control circuit is regular and the implementation can be derived in a systematic way. Therefore, the architecture can be easily applied to handle the convolutional code with a long constraint length and it is suitable to be implemented in VLSI applications.