Interconnection allocation between functional units and registers in High-Level Synthesis

Abstract

Data path connection elements usually consume a significant amount of both power and area on a VLSI chip. In this paper, we focus on the interconnection allocation problem conducted after operation scheduling and binding in High-Level Synthesis, aimed at minimum interconnection complexity, power consumption and area cost. During interconnection allocation, the port assignment step, that connects the registers to the operator ports through multiplexers (MUXes), is extraordinarily crucial to the final result in terms of the interconnection complexity. We formulate the port assignment problem for binary commutative operators as a bipartite graph partition problem followed by a vertex cover, and adopt the Fiduccia and Mattheyses (FM) Algorithm to iteratively improve the partition by moving or swapping the graph vertices. The experimental results show that our proposed algorithm is able to achieve 35.9% optimality increasing and 33.1% execution time reduction compared with the previous works.