Implementation of integrated design space exploration of scheduling, allocation and binding in high level synthesis using multi structure genetic algorithm

Michael Gebremariam

doi:10.32920/ryerson.14655717.v1

Abstract

The objective of this project is to develop a software tool which assists in comparison of a work known as "M-GenESys: Multi Structure Genetic Algorithm based Design Space Exploration System for Integrated Scheduling, Allocation and Binding in High Level Synthesis" with another well established GA approach known as "A Generic Algorithm for the Design Space Exploration of Data paths During High-Level Synthesis". Two sets of software are developed based on both approaches using Microsoft Visual 2005 C# language. The C# language is an object-oriented language that is aimed at enabling programmers to quickly develop a wide range of applications on the Microsoft .NET platform. The goal of C# and the .NET platform is to shorten development time by freeing the developer from worrying about several low level plumbing issues such as memory equipment, type safety issues, building low level libraries, array bound checking, etc., thus allowing developers to actually spend their time and energy working on the application and business logic.

Highlights

Advances in VLSI technology have made high-level synthesis process more complicated
The objective of this project is to develop a software tool which assists in comparison of a work known as "M-GenESys: Multi Structure Genetic Algorithm based Design Space Exploration System for Integrated Scheduling, Allocation and Binding in High Level Synthesis" with another well established GA approach known as "A Genetic Algorithm for the Design Space Exploration of Data paths During High-Level Synthesis"
High-level synthesis process involves three interdependent and NP-complete optimization problems: (i) Operation scheduling (ii) Resource allocation (iii)Synthesis Evolutionary algorithms have been effectively employed to high level synthesis in existence of conflicting design objectives for finding good tradeoffs in the design space exploration

Summary

Introduction

Advances in VLSI technology have made high-level synthesis process more complicated. Recent advances in high-level synthesis have to find the most effective approach to deal with the complexity of today's increasing System-on-Chip (SoC) design demand. In the case of high level synthesis, performing design space exploration to choose the best candidate architecture by concurrently satisfying many operating constraints and optimization parameters is considered the most important stage in the whole design flow. Since the design space is huge and complex, there needs to be an efficient way to explore the best candidate architecture for the system design based on the application to be executed. Recent advancements in areas of communications and multimedia have led to the growth of a wide array of applications requiring huge data processing at minimal power expense. Such data hungry applications demand satisfactory performance with power efficient hardware solutions. Since the selection process for the best design architecture is complex, an efficient approach to explore the design space for selecting the best design option is needed

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Conclusion