Interconnect Geometry Optimization Using Modular Artificial Neural Networks

Abstract

This paper describes a methodology for crosstalk prediction and minimization in interconnect wiring using artificial neural networks. Neural networks are used as parameterized models to achieve two important mappings. The first—forward map—maps the geometric and material parameters of interconnects (for example width, length, separation, conductivity, dielectric constant k) to equivalent electrical parameters (for example, R,L,C,G). Such a relationship would normally require quasi-TEM solutions of EM problems. The second—reverse map—is the reverse of the first mapping equivalent electrical parameters to interconnect geometric and material parameters. The crosstalk minimization approach proposed involves topological decomposition of interconnect into standard cells—portions of interconnect referred to as wirecells—and the derivation of the above two mappings for each wirecell. Crosstalk is iteratively minimized in the domain of SPICE circuit parameters and the resulting optimized SPICE equivalent circuit mapped back into the wirecell geometric domain using the reverse neural net mapping. For computational efficiency and high accuracy, the technique initially establishes a library of re-usable neural wirecell models using a field solver coupled with a circuit simulator and a neural network multi-paradigm prototyping system. The approach offers two important advantages. First, the simultaneous effect of multiple non-correlated geometric and material wirecell characteristics on crosstalk can be accurately computed and crosstalk minimized by iterative modification of interconnect geometry and material characteristics. Second, the approach produces—as a by-product—system level contours of equicoupling called isocouples to guide design activities such as placement and route. Crosstalk prediction and minimization results are presented for a high performance operational transconductance amplifier in which reduction in crosstalk by variation of interconnect layout geometry resulted in a 41% increase in gain.