Interconnect Fatigue Failure Parameter Isolation for Power Device Reliability Prediction

Abstract

Flip chip (FC) packaging techniques in modern power electronics have enabled increased power density in module performance, but mechanical stresses induced by thermal expansion during inherent operating conditions in the power devices and packages create a need for understanding thermomechanical fatigue mechanisms that lead to reliability concerns. Moreover, in actual use, these mechanical stresses impact the reliable lifetime alongside thermal factors (such as diffusion and microstructural transformation) and other process history effects. This amalgam of damage inducing phenomena make development of a concise association between damage, fatigue, and stress factors difficult to determine. For reliability demonstration under fatigue loading, accelerated life testing (ALT), such as Thermal Cycling (TC), are commonly used in industry; however, long duration and expensive equipment required for TC limit its utility, especially when considering the high cost of wide-bandgap devices and modules, and the limitation of high temperature (> 150°C) testing standards. As a result, alternative test methodologies are needed to provide faster, cheaper, and design integrable reliability determination. In this work, an accelerated test methodology is introduced and designed to simulate these mechanical stresses at isothermal conditions, which is demonstrated using test chips that are analogous to power devices. By stressing these devices in a controlled environment, mechanical stresses become de-coupled from the design and temperature, such that useful lifetimes can be predictable. Mechanical shear stress was cyclically applied directly to device-relevant, flip-chip solder interconnects while monitoring cycles-to-failure (CTF). Also, Finite Element Analysis (FEA) is used to extract various damage metrics of different solder materials (including PbSn37/63, SAC305 and Nano-silver) in both thermal operation and the introduced alternative mechanical testing conditions. In doing so, test protocol translations to common qualification tests (or use condition thermal profiles) can be determined and are validated using the mechanical shear stress testing method. Plastic work density and maximum shear were calculated in the critical solder interconnects for different isothermal mechanical testing temperatures (22°C, 75°C, 100°C and 125°C) and the results are compared with the simulation results of different TC test conditions. This reliability determination with failure parameter isolation allows for improved integration with FEA modeling for a priori reliability prediction during the design process.