Solder joint reliability analysis for large size WLCSP

Abstract

Wafer-level chip-scale package (WLCSP) with solder joint as interconnection process was used to enable, thinner, low cost and fine-pitch for mobile type of information and communication device that assembly into SiP module. However, the lower solder joint reliability performances is the key challenge and more and more serious as increasing WLCSP package size, especially the size is larger than 6mm × 6mm. In this work, a three-dimensional finite element model and the Anand's visco-plasticity Model is used to simulate solder's creep behavior under thermal cycling test condition was constructed and experimentally benchmarked to qualitatively figure out solder joint failure location in whole package and crack position in solder interconnection. Besides, the plastic work density (PWD) accumulated per temperature cycle at the solder joint/Cu pad interface is used to evaluate the risk of solder fatigue cracking failure. To observe the correlation between solder joint fatigue reliability and Δ PWD, it shows that the reliability decreases as increasing Δ PWD. Hence, the targeted on minimized solder joint's plastic work density (PWD), a design for the package structure with die thickness, dielectric layer thickness, and solder supporting thickness was also studied. Results indicate that the lower structure flexural rigidity (thinner die), stress buffer enhancement, and solder joint protection to follow in order to enhance solder thermal cycling reliability. This work provides a design guideline for structure optimization to satisfactory board level reliability.