Interconnect effects on thermal resistance of CMOS-SOI transistors in microwave power integrated circuits

Abstract

Thermal resistance (Rth) is an important design parameter for high power integrated circuits (ICs). Evaluation of Rth is particularly complicated for FETs in CMOS silicon-on-insulator (SOI) technology. Although the buried oxide underneath FETs in CMOS ICs presents a barrier to heat flow, the interconnect metals and surrounding oxide provide additional paths for heat-sinking. This paper describes simulations of the layout-dependent Rth of FETs in a CMOS-SOI IC including the interconnect effects, and experimental measurements that support the simulated results. The simulation technique used is an adaptation of a commercial electromagnetic solver, EMX, to heat flow. Simulation results show that in representative layouts with power FETs the heat flow via interconnects accounts for 50 to 70% of the overall heat flow in typical microwave and millimeter-wave ICs. Analytical results are presented to allow estimation of various Rth contributions. Experimental measurements are reported using I-V characteristics of a p-n diode to monitor the temperature of an FET, in good agreement with the analysis. Guidelines for the reduction of Rth are discussed. A layout technique for reducing Rth of an FET is described, and demonstrated experimentally by I-V measurements. The benefit of vias through the buried oxide is highlighted.