Interconnect Design and Benchmarking for Charge-Based Beyond-CMOS Device Proposals

Abstract

This letter presents a uniform interconnect-centric benchmark methodology for various emerging charge-based device technologies, including ferroelectric FETs, tunneling FETs, piezoelectric FET, graphene pn junction, and 2D material-based FET. Multiple key metrics are proposed and implemented to quantify the circuit/system limitations imposed by repeaters and interconnects. The results in this letter give device technologists an insightful perspective to better balance and manage the trade-offs of intrinsic device properties for the optimum interconnect performance.