Interconnect and circuit modeling techniques for full-chip power supply noise analysis

Abstract

This paper describes the interconnect and circuit modeling techniques to analyze the on-chip power supply noise for high-performance very large scale integration (VLSI) design. To reduce the complexity of full-chip analysis, a hierarchical power supply distribution model, which consists of a 12/spl times/12 package model, a 50/spl times/50 on-chip power bus model, and a distributed switching circuit model, is developed. This integrated chip-and-package model provides a complete analysis of the resistive IR drop, inductive delta-I noise, and the on-chip Vdd distribution. It also allows designers to identify the hot spots on the chip and optimize design variables to minimize the noise. Analysis results of our benchmark microprocessor chips will be presented to demonstrate the various applications of this methodology.