Inter-channel offset and gain mismatch correction for time-interleaved pipelined ADCs

Abstract

This paper presents a digital background calibration technique to compensate inter-channel gain and offset errors in parallel, pipelined analog-to-digital converters (ADCs). By using an extra analog path, calibration of each ADC channel is done without imposing any changes on the digitizing structure, i.e., keeping each channel completely intact. The extra analog path is simplified using averaging and chopping concepts, and it is realized in a standard 0.18 ‐ μ m CMOS technology. The complexity of the analog part of the proposed calibration system is same for a different number of channels. Simulation results of a behavioral 12-bit, dual channel, pipelined ADC show that offset and gain error tones are improved from −56.5 and −58.3 dB before calibration to about −86.7 and −103 dB after calibration, respectively.