Intelligent Mapping Method for Power Consumption and Delay Optimization Based on Heterogeneous NoC Platform

Juan Fang,Huayi Cai,Huan Zong,Haoyan Zhao

doi:10.3390/electronics8080912

Abstract

As integrated circuit processes become more advanced, feature sizes become smaller and smaller, and more and more processing cores and memory components are integrated on a single chip. However, the traditional bus-based System-on-Chip (SoC) communication is inefficient, has poor scalability, and cannot handle the communication tasks between the processing cores well. Network-on-chip (NoC) has become an important development direction in this field by virtue of its efficient transmission and scalability of data between multiple cores. The mapping problem is a hot spot in NoC's research field, and its mapping results will directly affect the power consumption, latency, and other properties of the chip. The mapping problem is a NP-hard problem, so how to effectively obtain low-power and low-latency mapping schemes becomes a research difficulty. Aiming at this problem, this paper proposes a two-populations-with-enhanced-initial-population based on genetic algorithm (TI_GA) task mapping algorithm based on an improved genetic algorithm from the two indexes of power consumption and delay. The quality of the initial individual is optimized in the process of constructing the population, so the quality of initial population is improved. In addition, a two-population genetic mechanism is added during the iterative process of the algorithm. The experimental results show that TI_GA is very effective for optimizing network power consumption and delay of heterogeneous multi-core.

Highlights

This paper proposes a two-populations-with-enhanced-initial-population based on genetic algorithm (TI_GA) task mapping algorithm based on an improved genetic algorithm from the two indexes of power consumption and delay
When dealing with the application requirements of large data size and high real-time requirements, the system platform of multi-core processors working together shows great advantages compared with the single core processor system platform, but it poses a great challenge to the on-chip system communication capabilities
We have suggested a two-population genetic algorithm (TI_GA) to optimize the initial

Summary

Introduction

When dealing with the application requirements of large data size and high real-time requirements, the system platform of multi-core processors working together shows great advantages compared with the single core processor system platform, but it poses a great challenge to the on-chip system communication capabilities. A serious challenge for NoC designers is how to create a preferable algorithm to achieve mapping solutions with low-power consumption and low-latency [8]. Several NoC mapping algorithms for optimizing energy consumption or time delay have been proposed. NoC mappinghave algorithms for obtaining a low energy consumption communication achieved these algorithms lower power consumption or higher performance, these papers weighted model. The mapping schemes achieved by these algorithms lower discuss single optimization targets of NoC, and are not applicable to the multi-targethave mapping power consumption or higher performance, these papers discuss single optimization targets of. 3, a mathematical model of power consumption delay is established, and in4,Section proposed, and the algorithms introducedintroduced in detail.

Two-Step of NoC Mapping

Establishment of Mapping Evaluation

Power Model

Delay Model

Multi-Objective Mapping Optimization Model

Mapping Algorithm Steps from Task to IP Core

Mapping Algorithm Steps from IP Core to NoC Platform

Performance Analysis

This ratio represented

Findings

Conclusions