Abstract
This paper outlines yield improvements in the integration of damascene copper in low-k SiCOH intermetal dielectric at 65 nm dimensions. Large defect reductions were seen by RIE, wet cleans and CMP process optimization. RIE improvements led to reductions of thirty three percent for missing pattern defects while wet clean optimization resulted in more than a fifty percent reduction in metal voids. CMP carrier head changes provided a more corrosion resistant process and higher throughput. Additionally, a high performance M1 module that maintained process window for all sectors was developed.
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