Abstract
PANDA is a key experiment of the future FAIR facility and the Micro Vertex Detector (MVD) is the innermost part of its tracking system, designed to identify primary and secondary vertices. It will be composed of four concentric barrels and six forward disks, instrumented with silicon hybrid pixel detectors and double-sided microstrip detectors. The layout of the two strip barrels of the PANDA MVD foresees square and rectangular sensors, arranged in linear staves. The compact layout of the detector poses significant challenges on its integration. The staves consist of a carbon fiber support structure with an embedded cooling system. A complete stave has been used to perform a test of the cooling system, using resistors to simulate the power dissipation of the chips. A multilayer flexible bus will be used to connect the readout chips to the sensor, as well as to provide the interconnection between the various chips and to distribute the power supply to the chips and to the sensors. Different prototypes have been designed to explore the technology possibilities and to optimize the stave geometry.
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