Integration of Planarized Internally-Shunted Submicron NbN Junctions

Abstract

NbN-TaN-Nb(Ti)N non-hysteretic SNS Josephson junctions with Ta <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> N barriers tuned through nitrogen content at metal-insulator transition have been produced in a reliable way with characteristic voltage R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sub> I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> above 1.5 mV at 9 K. Barriers are typically 7-10 nm thick and Jc in the range 5 to 25 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> making feasible LSI RSFQ ADC circuit integration by using the lithographic tools of the Leti C-MOS platform. Junction tri-layers, NbTiN ground-plane and wiring levels have been reactively sputtered and optimized at 300°C in a reproducible way on 8-inch oxidized silicon wafers. A deep UV stepper combined with SF6 gas mixtures RIE has been used to achieve low spread lithography in junction diameters of 716 nm (3σ ~ 40 nm), of 465 nm (3σ ~ 84 nm) across the 8-inch. A well controlled CMP planarization process has been developed on thick PE-CVD silica layers deposited on each superconducting nitride layer. On-line FIB-SEM observations and electrical characterizations associated to the development of a technology test vehicle demonstrate the feasibility of the complete process. The reliable production of nitrides LSI RSFQ circuits such as ADCs and integrated imagers operating in a relaxed cryogenic environment in the 6-10 K temperature range is foreseen to open new telecoms and medical applications. Moreover, a new MgO-AlN-MgO layered insulating barrier junction is shown to operate above 10 K and will be developed for analog front-end circuit parts.