Integration of Low Temperature SiGe:B Raised Sources and Drains in p-Type FDSOI Field Effect Transistors

Abstract

Low temperature epitaxy is today necessary in thin film Fully Depleted SOI (FDSOI) MOSFETs in order to obtain good quality accesses. Indeed, high temperature process has been shown to be detrimental for the growth of raised sources and drains (RSD) on thin films, as dewetting of the starting film and/or islanding of the epitaxial layer can occur [1]. Besides, low temperature epitaxy is also a key enabler for 3D sequential CoolCubeTM integration, where the 3D fabrication of devices one on top of the other and on the same substrate requires low thermal budget processes (typically T<500°C) in order to avoid the degradation of the bottom layer [2]. However, development of low temperature epitaxy faces several challenges: contaminated starting surface, growth rate exponential decrease, lesser epitaxial layer quality or loss of selectivity over dielectrics to give few examples. In this work, through morphological observations and analysis of electrical devices, we will describe different approaches we use to solve these problems. Surface preparation is one of the most critical steps as it directly influences the subsequent epitaxy. Presence of contaminants (C, O, F mostly) can lead to lower growth rates and/or morphological defects in the epitaxial layer. High temperature H2 pre-bake (T>1000°C) yields H-passivated and contaminants-free surfaces, yet it is not compatible with thin films technologies. Nevertheless, native oxide can be removed using a “HF-last” wet clean as well, allowing a reduction in the pre-bake temperature necessary for a good surface preparation (750°C-775°C in [3]). Besides, native oxide can also be removed using the Siconi process, where a NH3/NF3 dry plasma transforms the oxide into a salt which can then be sublimated at temperatures below 200°C [4]. In our work, we show the influence of wet and dry cleans on the quality of the subsequent raised sources and drains epitaxy, the best surface being obtained when using both processes successively (Figures 1a to 1c). Using the optimum wet and dry cleans combination, the thermal budget of the H2 bake could then be reduced from two steps (650°C 2min + 750°C 30s) down to 650°C 2min only. Although higher concentration of interfacial contaminants is to be expected with a lower thermal budget H2 bake, we found no morphological degradation after our standard 650°C epitaxy of SiGe:B raised sources and drains. (Figure 1d). Additionally, equivalent electrical performances were obtained with the lower thermal budget bake (Figure 2). In a second time, the epitaxy temperature was also decreased. High order silanes (e.g. Si3H8, Si5H12) have been proposed to cope with the drastic Si growth rate decrease at low temperatures [5-6]. However, these liquid precursors are very costly, making them less appealing for industrial use. Meanwhile, use of germane (GeH4) and diborane (B2H6) also yields higher growth rates thanks to the preferential desorption of H atoms on B and Ge surface sites. Hence, SiGe:B epitaxy at 500°C was evaluated structurally in a previous work [7]. At such a low temperature, straightforward co-flow selective epitaxial growth (SEG) using chlorinated gases (SiH2Cl2 or HCl) is not possible anymore. Selectivity is then achieved using a deposition/etch (D/E) approach using Si2H6, GeH4 and B2H6 as growth precursors and HCl for the selective etching of polycrystalline materials on dielectrics. Good quality 2D epitaxial layers can thus be obtained with full selectivity over the buried oxide and the nitride gate spacer (Figure 1e). We also show that doubling the number of cycles (i.e. to D/E/D/E strategy) yields smoother access regions, yet at the cost of the selectivity (Figure 1f). Use of more reactive chlorine gas is therefore proposed to obtain desired selectivity at 500°C. Finally, for the first time, pMOSFETs on thin SOI (tSi=11nm) substrate were fabricated using the new 500°C D/E recipe for SiGe:B raised sources and drains and functional transistors were obtained (Figure 3). A thorough electrical analysis of these devices (e.g. access resistance, mobility) will be provided in this work. [1] Y. Ishikawa et al., Appl. Surf. Sci. 90, 11-15, 2002. [2] P. Batude et al., Proceedings of 2015 VLSI Technology Symposium, 48-49, 2015. [3] A. Abbadie et al., Appl. Surf. Sci. 225, 256-266, 2004. [4] M. Labrot et al., Appl. Surf. Sci. 371, 436-446, 2016. [5] A. Gouyé et al., Appl. Phys. Lett. 96, 063102, 2010. [6] J. C. Sturm et al., ECS Trans. 16 (10), 799-805, 2008. [7] J-M. Hartmann et al., ECS J. Sol. State Sci. Technol. 3, 382-390, 2014. Figure 1