Abstract

A device associating a GaAs/ GaAlAs heterojunction FET with a CdTe photoconductor is presented. FET optimization criteria yielding maximum transconductance have been determined and the C gs / G m ratio has been evaluated. The successive technological steps highlight the thermal compatibility of the method of fabrication. The dimensions of our transistor are as follows: 5 μm X 350 μm gate length and width respectively. The photoconductor with an area of 100 μm X 100 μm has three sets of interdigitated ohmic contacts with 10 μm spacing between the fingers. FET transconductance values over 25 mS/mm have been achieved. The integrated circuit presents a responsivity I out / P opt as high as 30 A/W while that of the photoconductor is 2 A/W at 4 V gate bias. The Hall measurement of the CdTe layer gives a mobility of 270 cm 2/ V· s at room temperature and a resistivity of 100 Ω cm.

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