Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning

Abstract

Photoresist (PR) trimming for narrowing gate critical dimensions (CD) to sub-50 nm range is a known technique in polysilicon gate CMOS technology. However, the trend to replace polysilicon by a suitable metal such as TaN involves replacement of PR mask by a dielectric hard mask (HM) for providing tight CD and profile control in subsequent TaN etching. We have found that traditional selective etching of dielectrics on top of TaN film poses many challenges. Besides, PR trimming also should be tuned so that PR mask after trimming could match requirements of HM etching. By study and optimization of both PR trimming and HM etching in dipole ring magnetron etcher, we developed a production worthy processes for fabrication of sub-50 nm hard mask used for TaN gate etching in CMOS technology.