Abstract

The anisotropic etching release of a silicon microcantilever structure becomes challenging when it has embedded metal layers. We integrated the anisotropic wet silicon etching and etch-back method for the microcantilever releasing process in a silicon-on-insulator (SOI) wafer using a planar molybdenum (Mo)-based mask. Mo mask, which has good stability on morphology in tetramethylammonium hydroxide (TMAH) etchant as well as electrical characteristics, was employed to protect the metal resistor on the cantilever surface from TMAH etchant during silicon etching. To obtain a planar topography for the Mo mask, we applied a sequence of three etch-back processes using ZEP 520A resist, which has a similar etching rate to the non-doped silicate glass (NSG) layer in the plasma CF <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{4}$</tex-math> </inline-formula> :H <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{2}$</tex-math> </inline-formula> gas (40:1). After surface planarization, the angle of the indentation region (metal edge boundary area) was about 180 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> (almost flat), thus avoiding cracks in the Mo mask layer. As a result, the cantilever with a metal resistor was successfully released from the silicon substrate by our proposed method. Therefore, this process promises a silicon microcantilever fabrication method without backside alignment masks, relatively low temperature, and complementary metal-oxide semiconductor (CMOS) compatibility for chemical and bio-sensor applications.

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