Instruction-Level NBTI Stress Estimation and Its Application in Runtime Aging Prediction for Embedded Processors

Abstract

Lifetime reliability management of miniaturized CMOS devices continuously gets more importance with the shrinking of technology size. Neither of existing design-time solutions (like guard-banding) and runtime methods (like reactive monitoring) does efficiently address this issue; rather, proactive approaches, which use runtime aging prediction, are getting more promising to provide resiliency. Among various reliability threatening mechanisms in recent technologies, negative bias temperature instability is the dominant factor; it depends on multiple time-varying operational parameters, including temperature, supply voltage, and stress. This paper proposes an efficient instruction-level stress estimation model; accordingly, it introduces a runtime aging prediction approach for embedded processors, taking simultaneous impacts of the temperature, supply voltage, and stress variations. We propose instruction degradation factor and architecture degradation factor metrics, respectively, for fine-grained stress estimation and recurring runtime aging prediction. We also provide a simulation environment for model validation. Simulation results of several benchmarks show that the proposed stress estimation model has an accuracy of about 92%, indicating that the method is accurate enough, yet simple for runtime usage.