Insertion of a Si layer to reduce operation current for resistive random access memory applications

Abstract

In this study, a reduction of low resistive state (LRS) current is discovered in a V:SiO2/Si bi-layer structure with the addition of a Si layer. A Pt/V:SiO2/TiN structure is fabricated as the standard sample. The results of conduction mechanism analyses for LRS indicate that a SiO2 interfacial layer forms through oxidation of the inserted Si layer after the set process. The LRS current reduction can be attributed to the formation of this SiO2 layer. In addition, self-compliance behavior for the bi-layer structure during the set process further proves the existence of this SiO2 buffer layer in LRS.