Input ordering for low power in CMOS logic gates

Abstract

The inputs of a gate that are logically equivalent (for example, the inputs of a two-input NAND gate) can have different power consumption associated with signal switching at the inputs because of differences in circuit topology. Since the power consumed by the gate is dependent on the switching frequency of the input signals, the input order (assignment of signals to logically equivalent gate inputs) can be optimized for power by assigning the signal with the highest switching frequency to the gate input which has the lowest power consumption. A detailed analysis is presented with both analytic and empirical models to show the difference in the power consumption that results from input ordering for a two-input NAND gate. Empirical evidence indicates that power savings of up to 40% may be possible in two-input NAND gates, with the potential for greater savings in NAND and NOR gates with larger numbers of inputs.