Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits

Abstract

We consider the use of necessary assignments for input lines, referred to as input necessary assignments, as part of a test generation process for path delay faults in standard-scan circuits. Input necessary assignments are computed in polynomial time and provide a unified framework for identifying undetectable faults and generating tests for detectable faults. Within this framework, large numbers of path delay faults can be considered efficiently and accurately. The proposed test generation procedure is able to resolve large numbers of path delay faults associated with the longest paths in benchmark circuits by detecting the faults using broadside tests or showing that they are undetectable by such tests. We also consider the use of input necessary assignments for test compaction.