Abstract
A test generation procedure for path delay faults is proposed that targets all path delay faults in the circuit-under-test. The procedure overcomes the difficulties in handling the exorbitant numbers of path delay faults in practical circuits by using a nonenumerative method of considering faults that never explicitly targets any specific path delay fault. Experimental results demonstrate the effectiveness of the method in deriving tests to detect very large numbers of path delay faults.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
