Input ESD Protection Networks for Fineline NMOS - Effects of Stressing Waveform and Circuit Layout

Abstract

Human Body Model (HBM) and Charged Device Model (CDM) electrostatic discharge (ESD) stressing have been utilized to evaluate the susceptibility of input protection circuits on a fineline NMOS test chip. Failure analysis results and failure thresholds are reported as a function of local protection device parameters such as channel length and width and global layout variables such as power supply routing and circuit placement. It is demonstrated that the susceptibility to HBM stressing is determined primarily by protection device geometry. Failures occur by localized heating and filamentation across the channel. CDM failures, on the other hand, are sensitive to both local and global chip layout and occur primarily by damage to the thin gate oxide. In addition, CDM failure thresholds are much lower than those for the HBM case. These results are analyzed and a theoretical model for CDM failure developed on the basis of differences in protection device capacitance ratio and the critical charge for oxide breakdown due to Fowler-Nordheim tunneling.