Input Aware Lightweight Cryptosystem for IoT Infrastructure – Design, Implementation and Validation on Reconfigurable Hardware

Abstract

Listen

Translate article

The rise of IoT has also brought technological developments and threats. Edge computing has become a vital solution for most networks and demands resource-constrained operations. This work presents a lightweight data encryption scheme based on the Sierpinski Triangle Fractal, Chaotic Logistic map and their FPGA implementation on Intel Cyclone IV E. The size of the fractal geometry emerges from the number of bits in the input. Hence, this algorithm is an input-aware cryptosystem that simultaneously handles all input bits using rotation, random data fitting and diffusion. Further, round keys are supplied through the logistic map, and three incarnations of their FPGA implementations were investigated against randomness. Worst-case inputs have been taken to evaluate the design, and the results are validated through standard metrics. Round keys and cipher data have passed the NIST SP 800–22 test suites, thus evidence of the randomness. The proposed cryptosystem consumes only 944 logic elements (0.8%) and cipher 27/128/256 bits of data concurrently on Cyclone IV E FPGA. Encryption time has been calculated as 400 ns for 50 MHz of operating clock.