Abstract
Thanks to their outstanding electrical properties [1,2], carbon nanotubes (CNTs) are promising candidate to replace Cu in advanced interconnects [3–8]. In damascene based CNT via integration scheme, CNTs growth occurs on the whole surface of the wafers: in vias, but also on top surfaces [5]. CNTs on top are subsequently removed by polishing. In this paper, an alternative integration scheme is proposed which avoids CNTs on top. Thanks to careful choice of top surface (TiN) and bottom electrode (doped silicon) materials, CNT growth occurs only in vias. Dense growth (6 × 10 11 CNTs/cm 2) of small multi wall CNTs is achieved in vias over doped poly-silicon lines. Good encapsulation of CNTs is obtained with SACVD SiO 2 or ALD Al 2O 3 materials. Thanks to polishing of emerging CNTs, planarized CNT vias are obtained. Initial electrical measurements by conductive AFM show the conductivity of these CNT vias.
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