Abstract

Thermal stresses [1-4] in solder joint interconnections (see, e.g., [5]) used in electronic and photonic packaging are proportional to the thermal contraction mismatch strains T [3-9]. Here  is the effective coefficient of thermal expansion (CTE) mismatch between the soldered materials (the chip or the package to their substrates), and T is the change in temperature from the elevated manufacturing (bonding/fabrication/solder ing) temperature, at which, because of the interaction of shrinkage and stressrelaxation processes, the induced stresses are next-to-zero, to the low, room, testing or operation, temperature, at which the induced stresses are the highest. Clearly, these stresses are lower for lower soldering temperatures, and therefore there is an obvious incentive for using low temperature solders. What is less obvious is that significant stress relief in solder joints can be achieved also by employing, for the same materials and the same thermal mismatch strain T, inhomogeneous bonds [10-19], when, e.g., a solder material with a high soldering temperature and/or with a high Young’s/shear modulus is employed in the mid-portion of the assembly, where the stresses in this material are low (at the mid-cross-section of the assembly these stresses, distributed in an anti-symmetric fashion, are always zero), and a low-melting-point solder and/or a solder with a lower modulus is employed at the assembly’s peripheral portions, where the interfacial shearing and peeling thermal stresses are the highest. Ultimately, when only the elevated stresses, and not heat transfer considerations, are viewed to be critical, even assemblies bonded at the ends only are viable [16,17].

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