Abstract
We compared and analyzed accelerated soft error rate (ASER) for several cell structures and metal plate (MP) capacitor in the fabricated 16 mega static random access memory (SRAM). Application of the buried N-well (BNW) lowered the ASER value compared to the normal well and buried P-well (BPW) structure. By applying the new MP capacitor with the BNW in SRAM, the lowest ASER value can be obtained. The thinner oxide thickness of the MP capacitor provides higher capacitance and lower ASER value. The ASER is improved from 5492 failure in time (FIT) to 1030 FIT on 2.4 V after sole application of the BNW. However, it is dramatically improved to 15 FIT once the MP capacitor is additionally applied.
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