Influence of uniaxial tensile strain on the performance of partially depleted SOI CMOS ring oscillators

Abstract

The influence of uniaxial tensile strain on the performance of advanced partially depleted silicon-on-insulator CMOS ring oscillators is reported. Strain is applied either perpendicular or parallel to the direction of current flow by bending of thinned, fully processed wafers with a gate oxide thickness of less than 1.5 nm. Interestingly, the standby power dissipation of the ring oscillators increases for both parallel and perpendicular strains due to changes in the gate tunneling currents with strain. The on-state power dissipation decreases with parallel strain and increases with perpendicular strain consistent with the expected changes in the inversion layer piezoresistance. The speed of the ring oscillators improves with perpendicular strain and degrades with parallel strain, which can also be understood in terms of the piezoresistance changes.