Advanced Improvement in Speed of Operation of 3-Stage CMOS Ring Oscillator Clock Generation using CPG

Abstract

The Ring oscillator is a member of time delay Oscillators. In this Ring oscillator it uses odd number of inverters and has a gain greater than one. In normal Ring Oscillator architecture the performance is very low due to power gating mechanism. By using CPG technique the performance is increased and also utilizes low power for operation. This Ring oscillator by using CPG technique is affected by pressure and temperature variations. By using 3-stage CMOS ring oscillator the efficiency and performance is increased. In CMOS Ring oscillator power supervision (PS) and efficiency is increased. Most of the architecture is planned for cut back the ability within the IPs to provide power gating, with the task of falling system level control gating. In this CMOS Ring oscillator the output of each NOT gate is given to next stage in order to improve the system latency. For CMOS Ring oscillator, there is no output is given to system, but Reset pulse will drive the entire architecture. In CPG power of the device will change in cyclic manner, device will be ON and OFF over small duration of time. By this proposed method over all power consumption and speed of operation is increased.