Influence of Threshold Voltage Performance Analysis on Dual Halo Gate Stacked Triple Material Dual Gate TFET for Ultra Low Power Applications

Abstract

In this article, a two dimensional (2-D) threshold voltage modeling based gate and channel engineering are developed analytically for Dual Halo Gate Stacked Triple Material Dual Gate Tunnel FET (DH-GS-TM-DG-TFET) with effective surface charge. The model is derived by solving the 2-D Poisson equation in Silicon graded channel region using suitable boundary conditions. The proposed model incorporates the effects of various device parameters such as channel potential, electric field, DIBL, threshold voltage roll-off and drain current. Also, the fringing capacitance characteristics of the proposed DH-GS-TM-DG-TFET demonstrate superior performance over Triple material double gate and Single material double gate TFET structures. It is evident that the proposed device structure DH-GS-TM-DGTFET provides poor outflow current IOFF (10−16A/μm), and remarkable betterment in ON current (10−6A/μm). Moreover, the ION/IOFF ratio is 1010. To validate the robustness of model, the numerical results are compared with those obtained using Sentaurus TCAD.