Abstract
For a recessed gate (RG) silicon carbide ( SiC ) static induction transistor (SIT), an n-diffusion layer technique to maximize a maximum channel current ( I MAX ) and realize an efficient breakdown voltage (BV) was presented. An n-diffusion layer having a doping profile of a Gaussian distribution was formed from the source to the channel region and introduced to elevate the doping concentration of the channel region. Through the simulation of a RG SiC SIT with an n-diffusion layer, it was verified that an n-diffusion layer technique was an excellent way to realize a very small width of a source region ( W s ), resulting in an larger I MAX and a higher BV simultaneously, and it was desirable to employ an n-diffusion layer having a slightly larger junction depth ( X j ) than the depth of a gate trench ( L T ) ( L T < X j < 1.3 L T ) into a RG SiC SIT with a small width of the source region ( W S ≈ 0.5 μ m ).
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