Design optimization of 600 V SiC SITs for high power and high frequency operation

Abstract

For a recessed gate silicon carbide (SiC) static induction transistor (SIT), a new approach utilizing a supplementary highly doped region (SHDR) was demonstrated to achieve both high power capability and high operating frequency. Simulations for dc and small signal analysis were performed to optimize the SiC SIT structure for such purposes. The simulations showed that the SHDR-based architecture reduced the trade-off between breakdown voltage (BV) and maximum total current density (IMAX), resulting in a maximized power density (PD) and a higher cut-off frequency (ft) for a very small half-width of a source region (Ws). A 600 V SiC SIT with a SHDR was compared to an optimized conventional structure, showing that the proposed device structure possessed many advantages: greater IMAX capability, higher PD, greater transconductance (gm), higher ft and higher maximum frequency of oscillations (fmax). Consequently, both high power capability and high frequency response were achieved simultaneously, as long as a SHDR with a slightly larger junction depth (Xj) than the depth of a gate trench (LT)(LT < Xj < 1.2LT) was implemented into a conventional SiC SIT with a small Ws (Ws ≈ 0.25 µm).