Abstract
This work presents the influence of SiC epitaxial wafer quality on yield of 1.2kV SiC-DMOSFETs. Various wafer quality indicators were estimated by an integrated wafer quality evaluation system. SiC-DMOSFETs were fabricated on six 100 mm 4H-SiC epitaxial wafers. We show that the yield of SiC-DMOSFETs is related to threading screw dislocation density, defect density and bunched-steps length density evaluated by an integrated wafer quality evaluation system. A one-to-one analysis of multiple inspection data for SiC epitaxial defects and wafer-level electrical test results reveals the main factors in the yield of SiC- MOSFETs.
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