Influence of Etching-Induced Surface Damage on Device Performance With Consideration of Minority Carriers Within Diffusion Length From Depletion Edge

Abstract

The influence of etching-induced damage outside the depletion edge on the electrical characteristics of device is investigated using p-type metal-oxide-semiconductor structure with 2.5-nm SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectrics. It is found that surface defects act as generation centers when minority carrier concentration is below equilibrium, leading to the increase of diffusion current injecting into depletion region. The saturation current in inversion region is an order larger for damage located at 5 μm from the gate edge than that for damage free. On the contrary, the defects act as recombination centers when given light illumination. The saturation current in inversion region under illumination is reduced to one-fifth by etching-induced traps located at 5 μm from the gate edge with respect to that without etching due to the reduction of diffusion current. A semiempirical current model based on the lateral diffusion current due to the modulation of minority carrier concentration outside the depletion edge is in great agreement with the experimental results by quantitative simulation. The model is applicable to devices involving etching process or surface issues, especially for those in the submicrometer regime.