Influence of dc bias on the dielectric relaxation in Fe-substituted CaCu3Ti4O12 ceramics: grain boundary and surface effects

Abstract

CaCu3Ti4−xFexO12 (CCTFO, 0 ⩽ x ⩽ 0.2) ceramics were fabricated by the solid-state reaction method and the dielectric properties have been systematically studied. All ceramics showed the single cubic perovskite structure, and there was no secondary phase. The average grain size increased and the grain boundaries became thin and dense with increasing x. With increasing Fe doping content, the resistivity of grains and grain boundaries increased, which led to a decrease in ε′ in the frequency range from 1 kHz to 1 MHz. A new relaxation process II was discovered by means of dielectric properties spectra measurement at room temperature. Based on the internal barrier layer capacitance model, the dielectric relaxation process I originates from interfacial polarization at grain boundaries. The relaxation process II is sensitive to surface treatment and, in contrast to the relaxation process I, is also strongly affected by the dc bias. As the dc bias voltage increased up to 40 V, the low-frequency dielectric constant and resistivity decreased dramatically in the CCTFO (x = 0.01) ceramic. After polishing the surfaces of the CCTFO (x = 0.01) ceramic, ε′ decreased from 105 to 5 × 104 without the dc bias, but remained essentially unchanged with increasing dc bias voltage at low frequencies. The dependence of the dielectric properties on dc bias voltage and surface characteristics reveals that the relaxation process II originates from the interfacial polarization at the surface layers.