Abstract
Thick silicon carbide (SiC) epitaxial layers, which are required for the fabrication of SiC ultra-high voltage devices, have to be flattened by chemical mechanical polishing (CMP) in order to eliminate bunched-step segments, shallow pits, and epi-crowns. However, the negative effects of CMP on device performance is concerning. In this research, we attempted to evaluate a SiC epitaxial layer surface after flattening by CMP and to clarify the extent of CMP damage on the performance of a 4H–SiC PiN diode. As a result, a bundle of dislocation half-loops, which were detected by a mirror electron microscope (MEM) inspection system (Hitachi High-Technologies Mirelis VM-1000), was found to occur beneath the epitaxial layer surface flattened by CMP and led to current leakage of the PiN diode.
Published Version
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