Abstract
In this work, variations in the channel length and gate oxide thickness are studied for the design optimization of 3300 V 4H-SiC based VDMOSFETs. For this, a batch of 3 wafers was processed and tested for key device characteristics. The results indicate shorter channel length of 0.5 μm leads to an increase in the drain leakage current, thus affecting the breakdown voltage as well. The thinner gate oxide at 50 nm demonstrates better control of threshold voltage with no variations in the gate leakage current distribution as compared to 65 nm.
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