Influence of buffer layer thickness on memory effects of SrBi2Ta2O9∕SiN∕Si structures

Abstract

We deposited SrBi2Ta2O9 (SBT) thin films on silicon–nitride (SiN) buffered Si(100) substrates to form metal–ferroelectric–insulator–semiconductor structures and observed a significant influence of the buffer layer thickness on the magnitude and direction of the capacitance–voltage (C–V) memory window. As the SiN buffer layer thickness was decreased from 6nm to 2nm, the C–V memory hysteresis direction changed from memory direction dominated by ferroelectric polarization (i.e., counterclockwise for n-Si) to a trapping-related hysteresis direction (i.e., clockwise for n-Si). The memory windows for both cases exhibited a similar temperature dependence. The memory window approached zero at temperatures from 340°C to 380°C, which corresponds to the Curie temperature (TC) of the ferroelectric SBT films. When the temperature was returned to room temperature, the hysteresis windows were recovered. A detailed study has led us to believe that the switching of polarization of the ferroelectric SBT plays a key role in the observed temperature dependence, for both the ferroelectric polarization-dominated and the trapping-dominated memory window.