Inelastic electron tunneling spectroscopy study of traps in ultrathin high-k gate dielectrics

Abstract

We report the use of inelastic electron tunneling spectroscopy (IETS) as an effective tool in studying traps in high-k gate dielectrics, particularly the electrical stress-induced traps, in metal–oxide–semiconductor (MOS) structures. Two kinds of traps may be identified by the IETS technique: (1) those that contribute to trap-assisted conduction mechanisms and (2) those that contribute to trapping in the gate dielectric. These two kinds of traps can be distinguished from each other, because each of them exhibits a distinct feature in the IETS spectra. The trap energies are readily obtained from the voltage locations where these features occur. From voltage polarity dependence of the IETS spectra, one can get information about the spatial distribution of the traps. Examples will be shown to demonstrate the capability of the IETS technique for studying traps in MOS structures with high-k gate dielectrics.