Inductor Current Ripples Minimization in Coupled SIDO Buck and Buck-Boost Converter by Gate Pulse Shifting

Abstract

Single input dual output (SIDO) DC-DC converters are cost-efficient topologies to generate two outputs from a single input. The introduction of an inversely coupled inductor (CI) to the SIDO topologies further reduces the converter's physical size. The reduction of ripples is necessary for DC-DC converters. The shifting of gate pulses is used to reduce ripples in inductor currents of CI-SIDO boost converter. However, owing to the difference in the circuit topology, the analysis for the CI-SIDO boost may not apply to the CI-SIDO buck and buck-boost converter. So, this paper analyses CI-SIDO buck and buck-boost converter for all possible coupled inductor parameters and input, output voltages. The feasible slopes conditions are identified for both the converter. The minimum inductor current ripples of CI-SIDO buck and buck-boost converters are found by shifting gate pulses for each feasible condition. The range of gate pulse shift obtained is compared with the CI-SIDO boost. The converters are simulated in MATLAB/Simulink.