In-die overlay metrology method using SEM images

Abstract

We present an overlay measurement method that is designed to use scanning electron microscope (SEM) images taken in the circuit pattern region. In the semiconductor manufacturing, the overlay is currently measured using target patterns fabricated in the scribe line region. However, there are residual errors between the measurement values in the scribe line region and the actual values in the circuit pattern region. Therefore, in-die overlay accuracy measurements using circuit patterns are required for precise overlay control. We have developed an in-die overlay accuracy measurement method based on SEM images. The overlay is directly measured by comparing a golden image and a test image captured in the circuit pattern region. Each layer is automatically recognized from the images by utilizing a “graph cut” technique, and the placement error between the two images is determined and used to calculate the overlay accuracy. This enables us to measure the overlay accuracy without specially designed target patterns or the setting up of measurement cursors. In the numerical experiments using pseudoimages, the proposed method has linearity and sensitivity for the subpixel-order overlay even if the patterns have size variations. The basic performance of this method was evaluated using real SEM images. A measurement repeatability of less than 1.35 nm (0.36 pixel) was achieved, and a reasonable wafer map of the overlay was obtained.