Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment

Abstract

Timing closure remains one of the most critical challenges of a physical synthesis flow. Even if timing is almost closed at the end of the flow, last-mile placement and routing congestion optimizations may introduce new timing violations. Correcting such violations needs minimally disruptive techniques such as threshold voltage re-assignment and gate sizing that affect only marginally the placement and routing of the almost finalized design. To this end, we transform a powerful Lagrangian-relaxation-based optimizer, used for global timing optimizations at the early stages of the design flow, to a practical incremental timing optimizer that corrects small timing violations with fast runtime and without increasing the area/power of the design. By applying the proposed approach to the optimized designs of the ISPD 2013 gate sizing contest that experience new timing violations due to local wire rerouting, we improve timing by more than 36% on average, using 45% less runtime, when compared to the fully-fledged version of the timing optimizer.