Increasing the effective bandwidth of complex memory systems in multivector processors

Abstract

In multivector processors, the cycles lost due to memory interferences between concurrent vector streams make the effective throughput be lower than the peak throughput. Using the classical order, the vector stream references the memory modules using a temporal distribution that depends on the access patterns. In general, different access patterns determine different temporal distributions. These different temporal distributions could imply the presence of memory module conflicts even if the request rate of all the concurrent vector streams to every memory modules is less than or equal to their service rate. In addition, in a memory system where several memory modules are connected to each bus (complex memory system), bus conflicts are added to the memory module conflicts. This paper proposes an access order, different from the classical order, to reference the vector stream elements. The proposed order imposes a temporal distribution to reference the memory modules that reduces the average memory access time in vector processors with complex memory systems. When the request rate of all the vector streams to every memory module is greater than the service rate, the proposed order reduces the number of lost cycles, and the effective throughput increases. Under other conditions, the effective throughput reaches the peak throughput.