Increasing breakdown voltage of p-channel LDMOS in BCD technology with novel backside process

Abstract

A novel concept for a BCD technology is presented which comprises the processing of the wafer on the thinned backside and which offers — similar to SOI technology — a full dielectric isolation of power devices. Limitations of the breakdown voltage of p-LDMOS encountered in conventional BCD technologies are overcome by replacing the commonly applied deep n well layer by an n+ region formed on the wafer backside and by connecting the n+ region with a TSV to the source potential on the front side. The fabricated p-LDMOS with drift length 5.7μm has a breakdown voltage (BVdss) of −115 V and an on-resistance (R on ) of 320 mΩ mm. It is found by TCAD simulations that further optimization of the p-LDMOS with respect to BVdss, Ron and electrical SOA can be achieved by adding an n-type RESURF layer below STI.